GS8342Q18E-300 sram equivalent, 36mb sigmaquad-ii burst of 2 sram.
* Simultaneous Read and Write SigmaQuad™ Interface
* JEDEC-standard pinout and package
* Dual Double Data Rate interface
* Byte Write controls sampled at .
where alternating reads and writes are needed. Therefore, the SigmaQuad-II SRAM interface and truth table are optimized .
Table
Symbol
SA NC R W
BW
Description
Synchronous Address Inputs No Connect
Synchronous Read Synchronous Write
Synchronous Byte Write
BW0
–BW3
Synchronous Byte Writes
NW0
–NW1
Nybble Write Control Pin
K Input Clock.
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